1. Technical Field
The present disclosure relates to integrated circuit (IC) chip fabrication, and more particularly, to air gap formation for metal-insulator interconnect structures for very large scale integrated (VLSI) and/or ultra-large scale integrated (ULSI) devices.
2. Background Art
Integrated circuit (IC) chips use air gaps within a dielectric material to increase the insulative characteristics of the dielectric material. One challenge facing the IC chip fabrication industry is protecting copper (Cu) interconnects within the dielectric material from exposure to processing steps during air gap fabrication at thin wires (e.g., <50 nm), which requires sub-ground rule lithography for any given technology generation. Current approaches use diblock copolymers as templates to form air gaps at thin wire levels. However, since copper (Cu) interconnects are not protected during this process, several reliability issues arise with this approach. Currently, there is no known solution to creating copper (Cu) exposure free thin wire air gaps using the diblock technology. One proposed approach opens holes in the dielectric material between copper (Cu) interconnects through a cap layer and extracts the dielectric material through the cap layer to minimize or avoid exposing copper (Cu) interconnects. Another dielectric material formed over the cap layer pinches off the opening to form the air gap. This approach uses wet etch techniques to extract the dielectric material remaining between the holes. This approach, however, is limited by the ability to damage and extract the dielectric material in the spaces between the holes. That is, the lithography required to pattern the holes has to be able to reach a level smaller than the spacing between the copper (Cu) interconnects, i.e., a level below currently available lithographic standards. For example, for 60 nanometer (nm) technology, spacing between interconnects is currently about 100 nm, so current 100 nm lithography technology typically results in exposing at least one of the interconnects.